In a flash memory, a transistor that configures a memory cell includes a charge accumulation layer of either a floating gate or an insulating film. The memory cell stores data by accumulating electrons in the charge accumulation layer. A silicon-oxide-nitride-oxide-silicon (SONOS) structure flash memory accumulates electrons in a nitride film of an oxide-nitride-oxide (ONO) film. U.S. Pat. No. 6,011,725 discloses a virtual ground flash memory having a virtual ground memory cell which is symmetrically operated by switching around a source and a drain.
FIG. 1A is a schematic top view of a conventional flash memory, and FIG. 1B is a schematic cross-sectional view taken along the line A-A of FIG. 1A. In FIG. 1A, a bit line 12 is shown through an ONO film 20. In FIG. 1A and FIG. 1B, the bit line 12 is formed in a semiconductor substrate 10. The ONO film 20 made of a tunnel insulating film 14, a charge accumulation layer 16, and a top insulating film 18 are formed on the semiconductor substrate 10. A word line 22 is formed on the ONO film 20 across the bit lines 12. The bit line 12 functions as either a source or a drain, and the word line 22 functions as a gate. A channel region 24 is formed at an area in the semiconductor substrate 10 between the bit lines 12 and below the word line 22.
By applying a high electric field between the source (B1) and the drain (B2), electrons flow through the channel region 24. In addition, electrical charges are accumulated in a charge accumulation region C1 of the charge accumulation layer 16. By switching around the source and the drain, electrical charges are accumulated in a charge accumulation region C2. As described above, by symmetrically operating the source and the drain, two charge accumulation regions can be formed in the charge accumulation layer 16 of a single transistor. Consequently, in one transistor, two bits can be stored.
In recent years, a demand for integration and miniaturization of memory cells has increased. In order to accommodate the trend, the space between the bit lines 12 or the distance between B1 and B2 needs to be narrowed. With the reduced space between the bit lines 12, the charge accumulation region C1 and the charge accumulation region C2 become close to each other. Consequently, isolating the two chare accumulation regions C1 and C2 becomes difficult. Due to the closeness of the two charge accumulation regions C1 and C2, the charges accumulated in the charge accumulation region C1 and in the charge accumulation region C2 interfere with each other. This is known as a complementary bit disturb (CBD).
FIG. 2A and FIG. 2B describe cross sectional views of a NAND flash memory designed to prevent charges accumulated in charge accumulation regions from interfering with each other. FIG. 3 is a schematic top view of the NAND flash memory illustrated in FIG. 2A and FIG. 2B. In FIG. 3, the charge accumulation layer 16 and such are omitted in the drawing.
In FIG. 3, an element isolating region 13, which is the cross-hatched area, is used to isolate source-drain regions 15 in the semiconductor substrate 10. In FIG. 2A, an oxide film 11 is formed on the semiconductor substrate 10. Then, the word line 22 is formed on the oxide film 11, and the charge accumulation layers 16 are formed at the periphery of the oxide film 11, as illustrated in FIG. 2B. In FIG. 2B, the word line 22 is formed on the oxide film 11.
As shown in FIG. 3, in the NAND flash memory, the source-drain regions 15 flank the word line 22. Therefore, an area between the source-drain regions 15 in the widthwise direction of the word line 22 becomes the channel region 24. Consequently, at both ends of the word line 22 adjacent to the source-drain regions 15, the charge accumulation regions are formed. Therefore, as shown in FIG. 2A and FIG. 2B, the phenomenon of the CBD can be prevented by separating the charge accumulation layers 16.
However, in the virtual ground flash memory of FIGS. 1A and 1B, the area below the word line 22 and between the bit lines 12 (e.g., B1 and B2) forms the channel region 24. Then, a charge accumulation region is formed in the charge accumulation layer 16 in the neighborhood of the bit line 12 in the lengthwise direction of the word line 22. Therefore, the method according to FIG. 2A and FIG. 2B used for the NAND flash memory cannot be used to separate the charge accumulation regions for the virtual ground flash memory.